Analog Mixed-Signal Receiver Front-End for High-Speed Wireline Transceivers

The increasing demand for high-performance AI computing requires data centers to process and return information at ever-faster speeds. Within each server, multiple dies inside a single chip package or chiplet architecture must communicate at high speed to keep pace with these processing demands. However, as data rates increase, channel loss on this die-to-die link causes TX signal attenuation and inter-symbol interference (ISI) at the receiver.



To recover the signal, this project designs an 8 Gb/s analog front-end receiver featuring a 4-bit Programmable CTLE, an 8-bit DAC, and a loop-unrolled DFE. The entire architecture is designed at the transistor level in a 45nm technology node and simulated across PVT corners and Monte Carlo simulation. All blocks were laid out using several matching-critical techniques, including common-centroid, interdigitation, dummy device addition, guard rings, and power grid distribution, and passed DRC and LVS, ready for post-layout simulation. These layout blocks were RC-extracted to verify and compare performance against the pre-layout simulation, enabling robust 8 Gb/s die-to-die communication.